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Tharunreddym/README.md

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About

I am an ASIC Verification and Embedded Validation Engineer focused on UVM testbenches, protocol validation, firmware testing, and Python automation.

I have hands on automotive embedded validation experience from Bosch India, where I worked on UART, SPI, I2C, and CAN validation, regression automation, protocol debugging, and hardware software integration.

I build ASIC verification projects using SystemVerilog, UVM, SVA, constrained random stimulus, scoreboards, reference models, functional coverage, and regression debug workflows.

I am pursuing my Masters in Computer Engineering at the University of Cincinnati and targeting roles in ASIC verification, design verification, embedded validation, firmware testing, and system level debug.


Technical Skills

ASIC Verification

SystemVerilog UVM SVA Constrained Random Functional Coverage Scoreboards Reference Models
Digital Systems

Verilog AXI4 RISC V RV32I SRAM DPI C
Embedded Validation

Embedded C STM32 FreeRTOS UART SPI I2C CAN UDS
Automation And Tools

Python pytest pyserial python can QuestaSim VCS Verdi Git Linux

Featured ASIC Verification Projects

AXI4 Memory Controller Verification

Built a UVM environment for AXI4 slave memory controller verification with agents, monitors, SVA checks, and scoreboard based validation across all 5 AXI4 channels.

Key validation areas

Write address Write data Write response Read address Read data Burst traffic Backpressure


Protocol Channels Methodology

RISC V Pipeline Verification

Developed a UVM testbench for a 5 stage RV32I pipeline with constrained random instruction generation, scoreboard checking, assertions, and a C++ reference model through DPI C.

Key validation areas

Forwarding Hazards Branches Pipeline stalls ALU operations Register writeback


Pipeline ISA Reference Model

SRAM Subsystem Verification

Built a UVM based SRAM verification environment with constrained random stimulus, SVA checks, and a shadow memory scoreboard for read and write data validation.

Regression evidence

22 simulations 20 random seeds 30K plus transactions Zero scoreboard mismatches 84.3 percent peak coverage


Regression Seeds Transactions

Featured Embedded Validation Projects

FreeRTOS Deadline Validation

Validated real time task behavior on STM32 with FreeRTOS using producer, processor, and monitor tasks. Added overload injection and Python based HIL style automation.

Key validation areas

Task timing Deadline misses Overload behavior UART logs pytest automation


Tests Platform RTOS

UDS Diagnostic Validation Suite

Built a Python based UDS diagnostic validation suite using python can, ISO TP, udsoncan, virtual CAN, and pytest regression tests.

Key validation areas

Diagnostic requests Positive responses Negative responses Virtual CAN ECU simulation


Tests Protocol Bus

Sensor Based Embedded Validation System

Validated STM32 and AHT30 sensor communication over I2C with UART logging, SDA and SCL fault injection, and recovery behavior checks.

Key validation areas

I2C reads Sensor data UART logs Fault injection Recovery testing


Tests Protocol Sensor

STM32 HIL Style Validation Bench

Created a Python automation bench for STM32 firmware validation with live UART capture, log parsing, guided fault injection, pytest regression, and HTML CSV JSON reports.

Key validation areas

UART capture Log parsing Fault injection Regression reports Firmware validation


Tests Reports Automation

What I Work On

class VerificationAndValidationEngineer:
    name = "Tharun R. Mopuru"
    location = "Cincinnati, Ohio"
    education = "Masters in Computer Engineering, University of Cincinnati"

    asic_verification = [
        "UVM testbench development",
        "SystemVerilog assertions",
        "Constrained random stimulus",
        "Scoreboards and reference models",
        "Functional coverage",
        "Regression debug"
    ]

    embedded_validation = [
        "Firmware validation",
        "Protocol debugging",
        "STM32 and FreeRTOS testing",
        "UART SPI I2C CAN validation",
        "Python automation",
        "HIL style test flows"
    ]

    target_roles = [
        "ASIC Verification Engineer",
        "Design Verification Engineer",
        "Embedded Validation Engineer",
        "Firmware Test Engineer"
    ]

Pinned Loading

  1. riscv-pipeline-verification riscv-pipeline-verification Public

    UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed…

    SystemVerilog

  2. axi4-verification axi4-verification Public

    AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

    SystemVerilog

  3. sram-uvm-verification sram-uvm-verification Public

    SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

    SystemVerilog

  4. UDS-Diagnostic-Validation-Suite UDS-Diagnostic-Validation-Suite Public

    UDS diagnostic validation suite using python-can, ISO-TP, and udsoncan with a threaded ECU simulator and pytest transport coverage.

    Python

  5. FreeRTOS-Deadline-Validation FreeRTOS-Deadline-Validation Public

    C

  6. STM32-HIL-Style-Validation-Bench STM32-HIL-Style-Validation-Bench Public

    Python