Pinned Loading

1. RISC-V-Pipelined-Core RISC-V-Pipelined-Core Public

   A 5-stage pipelined RV32I RISC-V processor in Verilog, verified in Vivado. Features a robust hazard unit with data forwarding, load-use stalling, and pipeline flush mechanisms.

   Verilog

2. CMOS-Inverter-Design-using-SKY130-PDK CMOS-Inverter-Design-using-SKY130-PDK Public

   A fully custom CMOS inverter designed using SKY130 open-source PDK, covering the schematic-to-layout flow. The design uses Xschem for schematic capture, Magic VLSI for layout, and ngspice for DC, t…

   1

3. RISC-V-Single-Cycle-Core RISC-V-Single-Cycle-Core Public

   Tcl