Skip to content
View Shreyasilver22's full-sized avatar
💭
Tapeout_2027
💭
Tapeout_2027
7 followers · 12 following
  • Delhi University Faculty of Technology
  • Delhi
  • 23:55 (UTC +05:30)

Block or report Shreyasilver22

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Shreyasilver22/README.md

⚙️ Shreyas Singh

RISC-V | ASIC Design | AI Robotics | Embedded Systems

🧠 About Me

       .___        __                  ________                
    __| _/____   |__| ____   ____    /  _____/  ____   ____   
   / __ |/  _ \  |  |/    \_/ __ \  /   \  ___ /  _ \ /    \  
  / /_/ (  <_> ) |  |   |  \  ___/  \    \_\  (  <_> )   |  \ 
  \____ |\____/  |__|___|  /\___  >  \______  /\____/|___|  / 
       \/                 \/     \/          \/            \/  
Hey there 👋 I’m Shreyas, an ECE engineer passionate about blending hardware design, AI, and embedded systems to build the brains behind the bots.
Currently exploring:

🧩 RISC-V architectures for low-power SoC design

⚡ ASIC design flows (RTL ➜ Layout ➜ Tape-out simulation)

🤖 AI-based robotics and self-stabilizing drones

⚙️ Tech Stack
Domain	Tools / Skills
💻 Languages	C / C++ / Python / Verilog / MATLAB
🧠 AI & Simulation	TensorFlow / Simulink / OpenCV
⚙️ VLSI Design	Cadence Virtuoso / Synopsys ICC2 / Tanner L-Edit
🔩 Hardware	Arduino Nano / ESP32 / MPU6050 / NRF24L01
🧬 Processor Design	RISC-V ISA / Pipeline Simulation / RTL-to-GDSII Flow

🚀 Projects & Experiments
🛸 Self-Stabilizing Drone Controller — MPU6050 + PID-based flight logic

🧮 8-bit ALU & Multiplier (RTL Synthesis) — Built using Synopsys Design Compiler

💾 SRAM & FinFET Simulations — Post-layout analysis with Silvaco

🤖 AI-Driven Object Tracker — Vision-based robotic arm control

⚡ Tiny RISC-V Core — My journey into open hardware ❤️

📊 GitHub Stats
<p align="center"> <img src="https://github-readme-stats.vercel.app/api?username=ShreyasSingh&show_icons=true&theme=tokyonight" alt="GitHub Stats" /> <br> <img src="https://github-readme-streak-stats.herokuapp.com/?user=ShreyasSingh&theme=tokyonight" alt="GitHub Streak" /> <br> <img src="https://github-readme-activity-graph.vercel.app/graph?username=ShreyasSingh&theme=tokyo-night" alt="GitHub Activity Graph" /> </p>
🐍 Contribution Snake
<p align="center"> <img src="https://raw.githubusercontent.com/ShreyasSingh/ShreyasSingh/output/github-contribution-grid-snake.svg" alt="Snake animation" /> </p>
🎧 Now Playing on Spotify
<p align="center"> <img src="https://spotify-github-profile.vercel.app/api/view?uid=YOUR_SPOTIFY_ID&cover_image=true&theme=novatorem&show_offline=false&background_color=121212&interchange=true" alt="Spotify Now Playing" /> </p>
🧩 Fun Zone
“Between circuits and code lies consciousness.”

ascii
Copy code
         .-.
        |_:_|
       /(_Y_)\
 .     ( \/M\/ )
  '.    '-| |-'    
    ':_   | |   _:
      '""' '"'""
💬 Random Fact: I once debugged an FPGA design at 3 AM listening to Don-Toliver No idea.
🎯 Goal: To design a neural-enabled RISC-V SoC for intelligent edge devices and have an ASIC tapeout by 2027.
🤖 Mood: "Make silicon think."

🔗 Connect with Me
<p align="center"> <a href="https://www.linkedin.com/in/YOUR-LINKEDIN-ID/"> <img src="https://img.shields.io/badge/LinkedIn-blue?logo=linkedin&logoColor=white" /> </a> <a href="mailto:yourmail@example.com"> <img src="https://img.shields.io/badge/Email-red?logo=gmail&logoColor=white" /> </a> <a href="https://github.com/ShreyasSingh"> <img src="https://img.shields.io/badge/GitHub-black?logo=github&logoColor=white" /> </a> </p>
<p align="center"> ⚡ *"From atoms to algorithms — I make both work together."* ⚡ </p> ```

Pinned Loading

  1. Digital-PID-controller-for-HOTPLATE Digital-PID-controller-for-HOTPLATE Public

    This repository is for the case study project done in DSC-14 Control Systems for B.Tech degree at Faculty of Technology, University of Delhi. It involves creating a PID controller but combing the p…

    Verilog 1

  2. Neural-Accelerator Neural-Accelerator Public

    This repository is related to the work done under the SEC project done in 5th semester by me

    Verilog 1 1

  3. DRONE_QUADCOPTER_STABLIZER_SEC_SEM_4 DRONE_QUADCOPTER_STABLIZER_SEC_SEM_4 Public

  4. Neural_Network_Hybrid_Optimizer-NNHO2025- Neural_Network_Hybrid_Optimizer-NNHO2025- Public

    A PyTorch implementation of a novel Hybrid Optimizer combining RMSProp with Particle Swarm Optimization (PSO). Achieves Adam-level performance on CIFAR-10 through dynamic swarm annealing and moment…

  5. RV32I-CPU-CORE-with-Custom-SCNN-acceleration RV32I-CPU-CORE-with-Custom-SCNN-acceleration Public

    This repository is related to the workd done for Sakec Hackathon 2026

    Verilog 1

  6. VLSI_Portfolio_Cadence_Analog_Digital_IC_Design VLSI_Portfolio_Cadence_Analog_Digital_IC_Design Public

    This repository contains all the designs done by Shreyas Singh in the VLSI related Labs-Digital VLSI design(5th semester) and Current Mode Analog VLSI desig(6th sem)

    1